Rapid Industrial Prototyping and Scheduling of 3G/4G SoC Architectures with HLS Methodology

In this paper, we present a Catapult C/C++ based methodology that integrates key technologies for high-level VLSI modelling of 3G/4G wireless systems to enable extensive time/area tradeoff study. A Catapult C/C++ based architecture scheduler transfers the major workload to the algorithmic C/C++ fixedpoint design. Prototyping experiences are presented to explore the VLSI design space extensively for various types of computational intensive algorithms in the HSDPA, MIMO-CDMA and MIMOOFDM systems, such as synchronization, MIMO equalizer and the QRD-M detector. Extensive time/area tradeoff study is enabled with different architecture and resource constraints in a short design cycle. The industrial design experience demonstrates significant improvement in architecture efficiency and productivity, which enables truly rapid prototyping for the 3G and beyond wireless systems.